Clock is not LVDS

Context

Input clock signals using LVDS signaling exhibits better physical characteristics. Although this project is a simple proof-of-concept, using a LVDS input interface adds a meaningful increase in complexity which is likely to be encountered in real-life applications.

Issue

The physical constraints editor GUI doesn't allow selecting a global clock input corresponding to a LVDS P/N pair. Forcing these pins in the PDC file wasn't attempted as the result is highly likely to result in failure.

Actions

• Look into the Polarfire 2 FPGA device documentation for design rules regarding LVDS global clock usage